The present invention relates to a circuit for maintaining the potential of a node point of a MOS dynamic circuit. The circuit of the present invention is applicable to, for example, a dynamic memory circuit.
In general, when a MOS dynamic circuit is used in such a manner that the potential of a node existing in the MOS dynamic circuit is supplied to a load circuit to control the operation of the load circuit, a problem is encountered in that the potential of the node tends to be lowered due to the occurrence of junction leakage current and tailing current in the transistors connected to the node, and, accordingly, the potential of the node against be maintained at a predetermined value. This problem is serious, particularly in the case where the frequency of the operation of the MOS dynamic circuit is low.
The junction leakage current is the leakage current which flows through a PN junction forming the source or drain of the MOS field effect transistors connected to the node. The tailing current is the leakage current which flows through the drain and the source of the transistor connected to the node under the condition that the gate-source voltage of said transistor is lower than the threshold voltage of said transistor.
A prior art circuit for maintaining the potential of a node is illustrated in FIG. 1. In the circuit of FIG. 1, a repetitive charging circuit 4' is connected to the node (ND). The repetitive charging circuit 4' comprises MOD field effect transistor 46 and the drain of the transistor 47 are connected to the supply source voltage V.sub.cc. The source of the transistor 46 is connected to the source of the transistor 47. The drain of the transistor 46 and the gate of the transistor 47 are connected to one electrode of the capacitor 48. A pumping clock signal 85 is supplied to the other electrode of the capacitor 48.
The repetitive charging circuit 4' of FIG. 1 operates as follows. When the potential of the node (ND) is HIGH and the potential of the signal S5 is LOW, the capacitor 48 is charged by the potential of the node (ND) through the transistor 46 with the voltage "V.sub.cc -V.sub.th ", where the V.sub.th is the threshold voltage of the transistor 46. After that, when the potential of the signal S5 becomes HIGH, the potential of the gate of the transistor 47 is raised higher than V.sub.cc and hence the transistor 47 turns completely ON, and accordingly the node (ND) is charged through the transistor 47 with the voltage V.sub.cc. At this time the transistor 46 is in an OFF state because the potentials of the source and the drain thereof are higher than the potential of the gate thereof. After that, when the potential of the signal S5 becomes LOW, the capacitor 48 is again charged. Thus, the above described processes re repeated. Only a small output current on the order of a nano-ampere is required of the repetitive charging circuit, because even such a small current is sufficient for compensating the leakage from the node (ND).
However, the prior art circuit of FIG. 1 cannot comply with the requirement that the potential of the node (ND) which is supplied to the load should be maintained higher than V.sub.cc. Such a requirement arises in the case of, for example, the dynamic memory circuit illustrated in FIG. 2 where the potential of the node of the circuit of FIG. 1 is used as the signal S(pc) which is supplied to the gates of the transistors Q.sub.4 and Q.sub.5 in the sense amplifier circuit of the dynamic memory circuit. The dynamic memory circuit of FIG. 2 comprises a set of bit lines BL(1) and BL(2), cells and dummy cells connected through transistors Q.sub.11, Q.sub.21 to the said bit lines, word lines (WL) and dummy word lines (DWL), a line for the signal S(R) and a sense amplifier circuit including the transistors Q.sub.1 and Q.sub.5.
In the dynamic memory circuit of FIG. 2, it is required that the potential of the signal S(pc) be higher than V.sub.cc. Usually the value of V.sub.cc is 5 volts and the value of S(pc) is 7 volts.
It has been known that, unless the potential of the signal, S(pc) is maintained at a predetermined value higher than Vcc, the dynamic memory circuit as illustrated in FIG. 2 will not operate correctly. For example, if the potential of the signal S(pc), i.e. the gate potential of the transistors Q.sub.4 and Q.sub.5, is lowered to V.sub.cc +V.sub.th, where V.sub.th is the threshold voltage of the transistors Q.sub.4 and Q.sub.5, the transistors Q.sub.4 and Q.sub.5 become OFF so that the bit lines BL(1) and BL(2) may not be shorted through the voltage source V.sub.cc.
In this state, if junction leakage current flows in the bit line BL(1) due to a small junction defect, the bit line BL(1) has a larger potential decrease than that of the bit line BL(2). Therefore, the potential relationship between the bit lines BL(1) and BL(2) may become the reverse of the correct relationship when the signal S(L) is applied to the gate of the transistor Q.sub.3 in the sense amplifier circuit.
Accordingly, there is a problem in that the potential of a predetermined portion of the dynamic memory circuit, such as illustrated in FIG. 2, cannot be maintained by using the prior art circuit of FIG. 1.
The prior art circuit for charging a node in a field effect transistor circuit is disclosed in, for example, the Japanese Patent Application Laid-open No. 54-160139 and the U.S. Pat. No. 3,986,044.